SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A

3.3-V ABT SCAN TEST DEVICES

WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS667B – JULY 1996 – REVISED JUNE 1997

2

POST OFFICE BOX 655303

description (continued)

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),

test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs

other testing functions, such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern

generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of ’LVTH182504A, which are designed to source or sink up to 12 mA, include equivalent 25-

Ω

series resistors to reduce overshoot and undershoot.

The SN54LVTH18504A and SN54LVTH182504A are characterized for operation over the full military

temperature range of –55

°C to 125°C. The SN74LVTH18504A and SN74LVTH182504A are characterized for

operation from –40

°C to 85°C.

B5

B6

B7

GND

B8

B9

B10

NC

B11

B12

B13

B14

GND

B15

B16

B17

A4

A5

A6

GND

A7

A8

A9

A10

NC

A11

A12

A13

GND

A14

A15

A16

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

28 29 30 31 32 33 34

87

6

5

4

93

1 68 67

2

35 36 37 38 39

66 65

27

64 63 62 61

40 41 42 43

SN54LVTH18504A, SN54LVTH182504A . . . HV PACKAGE

(TOP VIEW)

NC – No internal connection