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SN74LVT574PW Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVT574PW Datasheet(HTML) 2 Page - Texas Instruments |
2 / 15 page SN54LVT574, SN74LVT574 3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS139D – MAY 1992 – REVISED JULY 1995 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L ↑ H H L ↑ LL L H or L X Q0 H X X Z logic symbol† logic diagram (positive logic) OE 1D 2 1D 3 2D 4 3D 5 4D 6 5D 11 CLK 1Q 19 2Q 18 3Q 17 4Q 16 5Q 15 6Q 14 7Q 13 8Q 12 7 6D 8 7D 9 8D EN 1 OE CLK 1D 1Q 1 11 2 19 To Seven Other Channels 1D C1 C1 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC – 0.5 V to 4.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (see Note 1) – 0.5 V to 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage range applied to any output in the high state or power-off state, VO (see Note 1) – 0.5 V to 7 V . . . . Current into any output in the low state, IO: SN54LVT574 96 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74LVT574 128 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current into any output in the high state, IO (see Note 2): SN54LVT574 48 mA . . . . . . . . . . . . . . . . . . . . . . . . . SN74LVT574 64 mA . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK (VI < 0) – 50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, IOK (VO < 0) – 50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package 0.6 W . . . . . . . . . . . . . . . . . . . . DW package 1.6 W . . . . . . . . . . . . . . . . . . . PW package 0.7 W . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65 °C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150 °C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. |
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