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SN74LVC74ADT Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVC74ADT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 17 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) TG C C TG C C TG C C C TG C C PRE CLK D CLR Q Q C SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287S – JANUARY 1993 – REVISED MAY 2005 A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of these devices for down-translation in a mixed-voltage environment. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q 0 (1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC) 2 |
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