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SN54LVT125 Datasheet(PDF) 2 Page - Texas Instruments

Part No. SN54LVT125
Description  3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN54LVT125 Datasheet(HTML) 2 Page - Texas Instruments

   
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SN54LVT125, SN74LVT125
3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS
SCBS133D – MAY 1992 – REVISED JULY 1995
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE
A
Y
L
H
H
L
LL
H
X
Z
logic symbol
logic diagram (positive logic)
EN
1
1OE
2
1A
1Y
3
4
5
2A
10
9
3A
13
12
4A
2Y
6
3Y
8
4Y
11
2OE
3OE
4OE
1
4
56
2A
2Y
2OE
1
23
1A
1Y
1OE
10
98
3A
3Y
3OE
13
12
11
4A
4Y
4OE
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, and PW packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC
– 0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1)
– 0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, VO (see Note 1)
– 0.5 V to 7 V
. . . .
Current into any output in the low state, IO: SN54LVT125
96 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT125
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, IO (see Note 2): SN54LVT125
48 mA
. . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT125
64 mA
. . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0)
– 50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0)
– 50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): D package
1.25 W
. . . . . . . . . . . . . . . . . . . .
DB or PW package
0.5 W
. . . . . . . . . . . . .
Storage temperature range, Tstg
–65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150
°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.


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