SN54LV139A, SN74LV139A

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

SCLS396G – APRIL 1998 – REVISED JULY 2003

2

POST OFFICE BOX 655303

description/ordering information(continued)

These devices are designed for high-performance memory-decoding or data-routing applications requiring very

short propagation delay times. In high-performance memory systems, these decoders can minimize the effects

of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time

of these decoders and the enable time of the memory usually are less than the typical access time of the

memory. This means that the effective system delay introduced by the decoders is negligible.

The ’LV139A devices comprise two individual 2-line to 4-line decoders in a single package. The active-low

enable (G) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers

feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

outputs, preventing damaging current backflow through the devices when they are powered down.

FUNCTION TABLE

INPUTS

OUTPUTS

G

SELECT

OUTPUTS

G

B

A

Y0

Y1

Y2

Y3

H

X

X

H

H

H

H

L

L

LL

HH

H

L

L

HH

LH

H

L

H

LH

HLH

L

H

H

H

H

H

L