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CDK2308CITQ64 Datasheet(PDF) 2 Page - Cadeka Microcircuits LLC. |
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CDK2308CITQ64 Datasheet(HTML) 2 Page - Cadeka Microcircuits LLC. |
2 / 14 page ©2008 CADEKA Microcircuits LLC www.cadeka.com 2 PRELIMINARY Data Sheet Pin Assignments Pin No. Pin Name Description 1, 18, 23 DVDD Digital and I/O-ring pre driver supply voltage, 1.8V 2 CM_EXT Common Mode voltage output 3, 9, 12 AVDD Analog supply voltage, 1.8V 4, 5, 8 AVSS Analog ground 6, 7 IP0, IN0 Analog input Channel 0 (non-inverting, inverting) 10, 11 IP1, IN1 Analog input Channel 1 (non-inverting, inverting) 13 DVSSCLK Clock circuitry ground 14 DVDDCLK Clock circuitry supply voltage, 1.8V 15 CLKP Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave) 16 CLKN Clock input, inverting. For CMOS input on CLKP, bypass CLKN to ground with a 10nF capacitor 17, 64 DVSS Digital circuitry ground 19 CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high. 20 DFRMT Data format selection. 0: Offset Binary, 1: Two's Complement 21 PD_N Full chip Power Down mode when Low. All digital outputs reset to zero. 22 OE_N_1 Output Enable Channel 0. Tristate when high 24, 41, 58 OVDD I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V. 25, 40, 57 OVSS Ground for I/O ring 26 NC No Connect Pin Configuration TQFP-64 CDK2308 TQFP-64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 N/C N/C N/C 42 41 40 39 38 37 36 35 34 33 DVDDCLK CLKN CLKP DVSSCLK CLK_EXT |
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