SN54HCT32, SN74HCT32

QUADRUPLE 2-INPUT POSITIVE-OR GATES

SCLS064B – NOVEMBER 1988 – REVISED MAY 1997

1

POST OFFICE BOX 655303

Small-Outline (D), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW),

and Ceramic Flat (W) Packages,

Ceramic Chip Carriers (FK), and

Standard Plastic (N) and Ceramic (J)

300-mil DIPs

description

The ’HCT32 contain four independent 2-input OR

gates. They perform the Boolean function

Y

+ A • B or Y + A ) B in positive logic.

The SN54HCT32 is characterized for operation

over the full military temperature range of –55

°C

to 125

°C. The SN74HCT32 is characterized for

operation from –40

°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

Y

H

X

H

X

HH

L

L

L

1

1A

2

1B

1Y

3

4

2A

5

2B

2Y

6

9

3A

10

3B

3Y

8

12

4A

13

4B

4Y

11

≥1

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, N, PW, and W packages.

logic diagram (positive logic)

A

B

Y

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright

© 1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y

SN54HCT32 . . . J OR W PACKAGE

SN74HCT32 . . . D, DB, N, OR PW PACKAGE

(TOP VIEW)

32 1 20 19

910 11 1213

4

5

6

7

8

18

17

16

15

14

4A

NC

4Y

NC

3B

1Y

NC

2A

NC

2B

SN54HCT32 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection