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SN74GTL16612DLR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74GTL16612DLR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 13 page www.ti.com FEATURES SN54GTL16612 . . . WD PACKAGE SN74GTL16612 . . . DGG OR DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OEAB LEAB A1 GND A2 A3 VCC (3.3 V) A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC (3.3 V) A16 A17 GND A18 OEBA LEBA CEAB CLKAB B1 GND B2 B3 VCC (5 V) B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VREF B16 B17 GND B18 CLKBA CEBA DESCRIPTION/ORDERING INFORMATION SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED JULY 2005 • Members of Texas Instruments Widebus™ Family • UBT™ Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference • Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels • Support Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs • Identical to '16601 Function • Ioff Supports Partial-Power-Down Mode Operation • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port • Distributed VCC and GND Pins Minimize High-Speed Switching Noise • Latch-Up Performance Exceeds 500 mA Per JESD 17 The 'GTL16612 devices are 18-bit UBT™ transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. The user has the flexibility of using these devices at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT, OEC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1994–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535, all parameters are Instruments standard warranty. Production processing does not tested unless otherwise noted. On all other products, production necessarily include testing of all parameters. processing does not necessarily include testing of all parameters. |
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