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CT2-NL1MKTD53C Datasheet(PDF) 6 Page - JDS Uniphase Corporation |
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CT2-NL1MKTD53C Datasheet(HTML) 6 Page - JDS Uniphase Corporation |
6 / 8 page 6 OC-3 SFP TRANSCEIVER Timing of Status and Control Input/Output Parameter Symbol Condition Specification TX_DISABLE assert time t_off Time from rising edge of TX_DISABLE to when the Maximum 10 µs output optical power falls below 10% of nominal TX_DISABLE deassert time t_on Time from falling edge of TX_DISABLE to when the Maximum 10 µs output optical power rises above 90% of nominal Time to initialize t_init Upon power up or negation of TX_FAULT due to TX_DISABLE Maximum 300 ms TX_FAULT assert time t_fault Time from a fault condition to TX_FAULT assertion Maximum 100 µs TX_DISABLE for reset t_reset Time TX_DISABLE must be held HIGH to reset TX_FAULT Minimum 10 µs LOS assert time t_loss_on Time from loss of signal to assertion of LOS Maximum 100 µs LOS deassert time t_loss_off Time from non-loss condition to LOS deassertion Maximum 100 µs 2-wire serial clock rate f_serial_clock - Maximum 100 kHz Power Supply Voltage Parameter IR-1 LR-1 LR-2 Supply voltage Minimum 3.1 V 3.1 V 3.1 V Typical 3.3 V 3.3 V 3.3 V Maximum 3.5 V 3.5 V 3.5 V Power supply current drain1 Typical 222 mA 245 mA 245 mA Maximum 300 mA 300 mA 300 mA 1. Applies to hardware revision 2. Does not include output termination resistor current. |
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Similar Description - CT2-NL1MKTD53C |
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