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SN54ALS112A Datasheet(PDF) 1 Page - Texas Instruments

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Part No. SN54ALS112A
Description  DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN54ALS112A Datasheet(HTML) 1 Page - Texas Instruments

   
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SN54ALS112A, SN74ALS112A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS199A – APRIL 1982 – REVISED DECEMBER 1994
Copyright
© 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Fully Buffered to Offer Maximum Isolation
From External Disturbance
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
TYPE
TYPICAL MAXIMUM
CLOCK
FREQUENCY
(MHz)
TYPICAL POWER
DISSIPATION
PER FLIP-FLOP
(mW)
′ALS112A
50
6
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the
setup-time requirements is transferred to the
outputs on the negative-going edge of the clock
pulse (CLK). Clock triggering occurs at a voltage
level and is not directly related to the fall time of the
clock pulse. Following the hold-time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by tying
J and K high.
The SN54ALS112A is characterized for operation over the full military temperature range of – 55
°C to 125°C.
The SN74ALS112A is characterized for operation from 0
°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
LX
X
X
L
H
L
LX
X
X
H†
H†
H
H
LL
Q0
Q0
H
H
HL
H
L
H
H
LHL
H
H
H
H
H
Toggle
H
H
H
X
X
Q0
Q0
† The output levels in this configuration may not meet the
minimum levels for VOH. Furthermore, this configuration is
nonstable; that is, it does not persist when either PRE or
CLR returns to its inactive (high) level.
SN54ALS112A ...J PACKAGE
SN74ALS112A ...D OR N PACKAGE
(TOP VIEW)
SN54ALS112A . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND
VCC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
32 1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
2CLR
2CLK
NC
2K
2J
1J
1PRE
NC
1Q
1Q
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.


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