SN54ABTH162460, SN74ABTH162460

4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS241E – FEBRUARY 1993 – REVISED MAY 1997

7

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)(see Figure 1)

VCC = 5 V,

TA = 25°C

SN54ABTH162460

SN74ABTH162460

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

0

160

0

160

0

160

MHz

CLKAB high or low

3.8

3.8

3.8

Pl

CLKBA high or low

4.5

4.5

4.5

tw

Pulse

duration

LEAB1, 2, 3, or 4 high

2.8

2.8

2.8

ns

duration

LEBA high

2.8

2.8

2.8

LEB1, 2, 3, or 4 high

3

3

3

↑

A bus

2.5

2.5

2.5

Before CLKAB

↑

CE_SEL0/1

3.2

3.2

3.2

CLKENAB

3.2

3.2

3.2

Before LEAB1, 2, 3, or 4

↓

A bus

3.6

3.6

3.6

↑

B bus

3.8

3.8

3.8

↑

CLKENB

2.3

2.3

2.3

tsu

Setup time

Before CLKBA

↑

CLKENBA

2.5

2.5

2.5

ns

LEB1, 2, 3, or 4

4.3

4.3

4.3

SEL0/1

4.5

4.5

4.5

Before LEB1, 2, 3, or 4

↓

B bus

3.2

3.2

3.2

↓

B bus

4

4

4

Before LEBA

↓

LEB1, 2, 3, or 4

4.4

4.4

4.4

SEL0/1

4.3

4.3

4.3

↑

A bus

0.5

0.5

0.5

After CLKAB

↑

CE_SEL0/1

1.1

1.1

1.1

CLKENAB

0.5

0.5

0.5

After LEAB1, 2, 3, or 4

↓

A bus

1.2

1.2

1.2

↑

B bus

1.3

1.3

1.3

th

Hold time

After CLKBA

↑

CLKENB

1

1

1

ns

After CLKBA

↑

CLKENBA

1

1

1

SEL0/1

0

0

0

After LEB1, 2, 3, or 4

↓

B bus

1.5

1.5

1.5

After LEBA

↓

B bus

0.4

0.4

0.4

After LEBA

↓

SEL0/1

0.1

0.1

0.1

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.