Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

SN54ABT7819GB Datasheet(PDF) 3 Page - Texas Instruments

Part # SN54ABT7819GB
Description  512 횞 18 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
Download  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN54ABT7819GB Datasheet(HTML) 3 Page - Texas Instruments

  SN54ABT7819GB Datasheet HTML 1Page - Texas Instruments SN54ABT7819GB Datasheet HTML 2Page - Texas Instruments SN54ABT7819GB Datasheet HTML 3Page - Texas Instruments SN54ABT7819GB Datasheet HTML 4Page - Texas Instruments SN54ABT7819GB Datasheet HTML 5Page - Texas Instruments SN54ABT7819GB Datasheet HTML 6Page - Texas Instruments SN54ABT7819GB Datasheet HTML 7Page - Texas Instruments SN54ABT7819GB Datasheet HTML 8Page - Texas Instruments SN54ABT7819GB Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 20 page
background image
SN54ABT7819
512
× 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description
A FIFO memory is a storage device that allows data to be read from its array in the same order it is written. The
SN54ABT7819 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. Two independent
512
× 18 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate
empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag.
The SN54ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The state of the A0–A17 outputs is controlled by CSA and W/RA. When both CSA and W/RA are low, the outputs
are active. The A0–A17 outputs are in the high-impedance state when either CSA or W/RA is high. Data is
written to FIFOA–B from port A on the low-to-high transition of CLKA when CSA is low, W/RA is high, WENA
is high, and the IRA flag is high. Data is read from FIFOB–A to the A0–A17 outputs on the low-to-high transition
of CLKA when CSA is low, W/RA is low, RENA is high, and the ORA flag is high.
The state of the B0–B17 outputs is controlled by CSB and W/RB. When both CSB and W/RB are low, the outputs
are active. The B0–B17 outputs are in the high-impedance state when either CSB or W/RB is high. Data is
written to FIFOB–A from port B on the low-to-high transition of CLKB when CSB is low, W/RB is high, WENB
is high, and the IRB flag is high. Data is read from FIFOA–B to the B0–B17 outputs on the low-to-high transition
of CLKB when CSB is low, W/RB is low, RENB is high, and the ORB flag is high.
The setup- and hold-time constraints for the chip selects (CSA, CSB) and write/read selects (W/RA, W/RB)
enable and read operations on memory and are not related to the high-impedance control of the data outputs.
If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock cycle, the
chip select and write/read select can switch at any time during the cycle to change the state of the data outputs.
The input-ready and output-ready flags of a FIFO are two-stage synchronized to the port clocks for use as
reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOA–B (IRA) and the
output-ready flag of FIFOB–A (ORA). CLKB synchronizes the status of the input-ready flag of FIFOB–A (IRB)
and the output-ready flag of FIFOA–B (ORB). When the input-ready flag of a port is low, the FIFO receiving input
from the port is full and writes are disabled to its array. When the output-ready flag of a port is low, the FIFO that
outputs data to the port is empty and reads from its memory are disabled. The first word loaded to an empty
memory is sent to the FIFO output register at the same time its output-ready flag is asserted (high). When the
memory is read empty and the output-ready flag is forced low, the last valid data remains on the FIFO outputs
until the output-ready flag is asserted (high) again. In this way, a high on the output-ready flag indicates new
data is present on the FIFO outputs.
The SN54ABT7819 is characterized for operation over the full military temperature range of –55
°C to 125°C.


Similar Part No. - SN54ABT7819GB

ManufacturerPart #DatasheetDescription
logo
Texas Instruments
SN54ABT7819 TI1-SN54ABT7819 Datasheet
315Kb / 22P
[Old version datasheet]   CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SN54ABT7819 TI1-SN54ABT7819_13 Datasheet
315Kb / 22P
[Old version datasheet]   CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
More results

Similar Description - SN54ABT7819GB

ManufacturerPart #DatasheetDescription
logo
Texas Instruments
SN74ABT7819A TI-SN74ABT7819A Datasheet
321Kb / 21P
[Old version datasheet]   512 횞 18 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SN74ABT7819 TI-SN74ABT7819 Datasheet
284Kb / 20P
[Old version datasheet]   512 횞 18 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SN74ACT3638 TI-SN74ACT3638 Datasheet
461Kb / 30P
[Old version datasheet]   512 횞 32 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SN54ACT3632 TI-SN54ACT3632 Datasheet
383Kb / 25P
[Old version datasheet]   512 횞 36 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SN74ACT3638 TI1-SN74ACT3638_05 Datasheet
552Kb / 33P
[Old version datasheet]   512 횞 32 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SN74ACT3632 TI-SN74ACT3632 Datasheet
407Kb / 27P
[Old version datasheet]   512 횞 36 횞 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SN74ALVC7803 TI-SN74ALVC7803 Datasheet
196Kb / 14P
[Old version datasheet]   512 횞 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ABT7820 TI-SN74ABT7820 Datasheet
196Kb / 15P
[Old version datasheet]   512 횞 18 횞 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SN54ABT7820 TI-SN54ABT7820 Datasheet
199Kb / 14P
[Old version datasheet]   512 횞 18 횞 2 STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SN74ACT3631 TI-SN74ACT3631 Datasheet
378Kb / 26P
[Old version datasheet]   512 횞 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com