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SN54ABT3614HFP Datasheet(PDF) 7 Page - Texas Instruments |
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SN54ABT3614HFP Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 42 page  SN54ABT3614 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F – AUGUST 1995 – REVISED MAY 2000 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description reset The SN54ABT3614 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the empty flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high. A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high transitions of CLKA and FFB is set high after two low-to-high transitions of CLKB. The device must be reset after power up before data is written to its memory. A low-to-high transition on RST loads the almost-full and almost-empty offset register (X) with the value selected by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1. Table 1. Flag Programming FS1 FS0 RST ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X) H H ↑ 16 H L ↑ 12 L H ↑ 8 L L ↑ 4 FIFO write/read operation The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0–A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the A0–A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and FFA is high. Data is read from FIFO2 to the A0–A35 outputs by a low-to-high transition of CLKA when CSA is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2). Table 2. Port-A Enable Function Table CSA W/RA ENA MBA CLKA A0–A35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO1 write L H H H ↑ In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None L L H L ↑ Active, FIFO2 output register FIFO2 read L L L H X Active, mail2 register None L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high) The state of the port-B data (B0–B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0–B35 outputs are in the high-impedance state when either CSB or W/RB is high. The B0–B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIFO2 from the B0–B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, FFB is high, and either SIZ0 or SIZ1 is low. Data is read from FIFO1 to the B0–B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, EFB is high, and either SIZ0 or SIZ1 is low (see Table 3). |
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