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SN54ABT16823 Datasheet(PDF) 1 Page - Texas Instruments

Part No. SN54ABT16823
Description  18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN54ABT16823 Datasheet(HTML) 1 Page - Texas Instruments

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SN54ABT16823, SN74ABT16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS217C – JUNE 1992 – REVISED JANUARY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Members of the Texas Instruments
Widebus
™ Family
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D High-Impedance State During Power Up
and Power Down
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes
PCB Layout
D High-Drive Outputs (–32-mA IOH,
64-mA IOL)
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 18-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
The ’ABT16823 can be used as two 9-bit flip-flops
or one 18-bit flip-flop. With the clock-enable
(CLKEN) input low, the D-type flip-flops enter data
on the low-to-high transitions of the clock. Taking
CLKEN high disables the clock buffer, latching the
outputs. Taking the clear (CLR) input low causes
the Q outputs to go low independently of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Copyright
© 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-
ΙΙB are trademarks of Texas Instruments Incorporated.
SN54ABT16823 . . . WD PACKAGE
SN74ABT16823 . . . DGG OR DL PACKAGE
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1CLR
1OE
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2OE
2CLR
1CLK
1CLKEN
1D1
GND
1D2
1D3
VCC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2CLKEN
2CLK


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