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SN54ABT125 Datasheet(PDF) 1 Page - Texas Instruments

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Part No. SN54ABT125
Description  QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN54ABT125 Datasheet(HTML) 1 Page - Texas Instruments

   
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SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I – FEBRUARY 1997 – REVISED NOVEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Typical VOLP (Output Ground Bounce)
<1 V at VCC = 5 V, TA = 25°C
D High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D Ioff and Power-Up 3-State Support Hot
Insertion
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
SN54ABT125 ...J OR W PACKAGE
SN74ABT125 . . . D, DB, N, NS,
OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
VCC
4OE
4A
4Y
3OE
3A
3Y
32 1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
SN54ABT125 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
SN74ABT125 . . . RGY PACKAGE
(TOP VIEW)
114
78
2
3
4
5
6
13
12
11
10
9
4OE
4A
4Y
3OE
3A
1A
1Y
2OE
2A
2Y
description/ordering information
The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE) input is high.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74ABT125N
SN74ABT125N
QFN – RGY
Tape and reel
SN74ABT125RGYR
AB125
SOIC
D
Tube
SN74ABT125D
ABT125
–40
°C to 85°C
SOIC – D
Tape and reel
SN74ABT125DR
ABT125
SOP – NS
Tape and reel
SN74ABT125NSR
ABT125
SSOP – DB
Tape and reel
SN74ABT125DBR
AB125
TSSOP – PW
Tape and reel
SN74ABT125PWR
AB125
CDIP – J
Tube
SNJ54ABT125J
SNJ54ABT125J
–55
°C to 125°C
CFP – W
Tube
SNJ54ABT125W
SNJ54ABT125W
LCCC – FK
Tube
SNJ54ABT125FK
SNJ54ABT125FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.


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