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SMJ4C1024-10HL Datasheet(PDF) 9 Page - Texas Instruments |
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SMJ4C1024-10HL Datasheet(HTML) 9 Page - Texas Instruments |
9 / 27 page SMJ4C1024 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 5) (continued) ALT. ’4C1024-80 ’4C1024-10 ’4C1024-12 ’4C1024-15 UNIT SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT th(RLCA) Hold time, column address after RAS low (see Note 12) tAR 60 70 80 100 ns th(D) Hold time, data (see Note 10) tDH 15 20 25 30 ns th(RLD) Hold time, data after RAS low (see Note 12) tDHR 60 70 85 110 ns th(CHrd) Hold time, read after CAS high (see Note 13) tRCH 0 0 0 0 ns th(RHrd) Hold time, read after RAS high (see Note 13) tRRH 10 10 10 10 ns th(CLW) Hold time, write after CAS low (see Note 11) tWCH 15 20 25 30 ns th(RLW) Hold time, write after RAS low (see Note 12) tWCR 60 70 85 100 ns td(RLCH) Delay time, RAS low to CAS high tCSH 80 100 120 150 ns td(CHRL) Delay time, CAS high to RAS low tCRP 0 0 0 0 ns td(CLRH) Delay time, CAS low to RAS high tRSH 20 25 30 40 ns td(CLWL) Delay time, CAS low to W low (see Note 14) tCWD 20 25 40 50 ns td(RLCL) Delay time, RAS low to CAS low (see Note 15) tRCD 22 60 28 75 28 90 33 110 ns td(RLCA) Delay time, RAS low to column address (see Note 15) tRAD 17 40 20 55 20 65 25 80 ns td(CARH) Delay time, column address to RAS high tRAL 40 45 55 70 ns td(CACH) Delay time, column address to CAS high tCAL 40 45 55 70 ns td(RLWL) Delay time, RAS low to W low (see Note 14) tRWD 80 100 130 160 ns td(CAWL) Delay time, column address to W low (see Note 14) tAWD 40 45 65 80 ns td(RLCH)R Delay time, RAS low to CAS high (see Note 16) tCHR 20 25 25 30 ns td(CLRL)R Delay time, CAS low to RAS low (see Note 16) tCSR 10 10 10 15 ns td(RHCL)R Delay time, RAS high to CAS low tRPC 0 0 0 0 ns trf Refresh time interval tREF 8 8 8 8 ms tt Transition time (see Note 17) — — — — — ns NOTES: 5. Timing measurements in this table are referenced to VIL max and VIH min. 10. Referenced to the later of CAS or W in write operations. 11. Early-write operation only 12. The minimum value is measured when td(RLCL) is set td(RLCL) min as a reference. 13. Either th(RHrd) or th(CHrd) must be satisfied for a read cycle. 14. Read-modify-write operation only 15. Maximum value specified only to assure access time. 16. CBR refresh only 17. Transition times (rise and fall) for RAS and CAS are to be minimum of 3 ns and a maximum of 50 ns. |
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