SMJ320C25, SMJ320C2550

DIGITAL SIGNAL PROCESSOR

SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001

3

POST OFFICE BOX 1443

Terminal Functions

SIGNALS

I/O/Z†

DEFINITION

VCC

I

5-V supply pins

VSS

I

Ground pins

X1

0

Output from internal oscillator for crystal

X2/CLKIN

I

Input to internal oscillator from crystal or external clock

CLKOUT1

0

Master clock output (crystal or CLKIN frequency/4)

CLKOUT2

0

A second clock output signal

D15–D0

I/O/Z

16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/0 spaces.

A15–A0

O/Z

16-bit address bus A15 (MSB) through A0 (LSB)

PS,DS,IS

O/Z

Program, data, and I/O space select signals

R/W

O/Z

Read / write signal

STRB

O/Z

Strobe signal

RS

I

Reset input

INT2–INT0

I

External user interrupt inputs

MP/MC

I

Microprocessor/microcomputer mode select pin

MSC

0

Microstate complete signal

IACK

0

Interrupt acknowledge signal

READY

I

Data ready input. Asserted by external logic when using slower devices to indicate that the current bus

transaction is complete.

BR

0

Bus request signal. Asserted when the SMJ320C25 requires access to an external global data memory

space.

XF

0

External flag output (latched software-programmable signal)

HOLD

1

Hold input. When asserted, SMJ320C25 goes into an idle mode and places the data, address, and

control lines in the high-impedance state.

HOLDA

0

Hold acknowledge signal

SYNC

I

Synchronization input

BIO

I

Branch control input. Polled by BIOZ instruction

DR

I

Serial data receive input

CLKR

I

Clock for receive input for serial port

FSR

I

Frame synchronization pulse for receive input

DX

O/Z

Serial data transmit output

CLKX

I

Clock for transmit output for serial port

FSX

I/O/Z

Frame synchronization pulse for transmit. Configurable as either an input or an output.

† I/O/Z denotes input/output/high-impedance state.