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SMJ320C40 Datasheet(PDF) 5 Page - Texas Instruments

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Part No. SMJ320C40
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com

SMJ320C40 Datasheet(HTML) 5 Page - Texas Instruments

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SMJ320C40, TMP320C40
HOUSTON, TEXAS 77251–1443
NMI with bus-grant feature (C40 silicon revision
≥ 5.0)
The 320C40 devices have a software-configurable feature that forces the internal-peripheral bus to ready when
the NMI signal is asserted. This feature is not present in C40 silicon revision < 5.0. The NMI bus-grant feature
is enabled when bits 19–18 of the status register (ST) are set to 10b. When enabled, a peripheral bus-grant
signal is generated on the falling edge of NMI. When NMI is asserted and this feature is not enabled, the CPU
stalls on access to the peripheral bus if it is not ready. A stall condition occurs when writing to a full FIFO or
reading an empty FIFO. This feature is useful in correcting communication-port errors when used in conjunction
with the communication-port software-reset feature.
IDLE2 clock-stop power-down mode (C40 silicon revision
≥ 5.0)
The 320C40 has a clock-stop mode or power-down mode (IDLE2) to achieve extremely low power
consumption. When an IDLE2 instruction is executed, the clocks are halted with H1 being held high. To exit
IDLE2, assert one of the IIOF3–IIOF0 pins configured as an external interrupt instead of a general-purpose I/O.
A macro showing how to generate the IDLE2 opcode is given in Figure 2. During this power-down mode:
D No instructions are executed
D The CPU, peripherals, and internal memory retain their previous state.
D The external-bus outputs are idle. The address lines remain in their previous state, the data lines are in
the high-impedance state, and the output-control signals are inactive.
; ––––––––––––––––––––––––––––––––––––––––––––-–-–;
; IDLE2: Macro to generate idle2 opcode
; –––––––––––––––––––––––––––––––––––––––––––––-––;
Figure 2. Example of Software Subroutine Using IDLE2
IDLE2 is exited when one of the five external interrupts (NMI and IIOF3–IIOF0) is asserted low for at least four
input clocks (two H1 cycles). The clocks then start after a delay of two input clocks (one H1 cycle). The clocks
can start in the opposite phase; that is, H1 can be high when H3 was high before the clocks were stopped.
However, the H1 and H3 clocks remain 180
° out of phase with each other.
During IDLE2 operation, an external interrupt can be recognized and serviced by the CPU if it is enabled before
entering IDLE2 and asserted for at least two H1 cycles. For the processor to recognize only one interrupt, the
interrupt pin must be configured for edge-trigger mode or asserted less than three cycles in level-trigger mode.
Any external interrupt pin can wake up the device from IDLE2, but for the CPU to recognize that interrupt, it must
also be enabled. If an interrupt is recognized and executed by the CPU, the instruction following the IDLE2
instruction is not executed until after execution of a return opcode.
When the device is in emulation mode, the CPU executes an IDLE2 instruction as if it were an IDLE instruction.
The clocks continue to run for correct operation of the emulator.

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