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SMJ320C6201BGLP Datasheet(PDF) 4 Page - Texas Instruments |
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SMJ320C6201BGLP Datasheet(HTML) 4 Page - Texas Instruments |
4 / 73 page SM320C6201, SMJ320C6201B DIGITAL SIGNAL PROCESSORS SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Signal Descriptions (Continued) SIGNAL TYPE† DESCRIPTION NAME NO. TYPE† DESCRIPTION EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 Y5 O/Z CE2 V3 O/Z Memory space enables CE1 T6 O/Z • Enabled by bits 24 and 25 of the word address CE0 U2 O/Z • Only one asserted during any external data access BE3 R8 O/Z Byte enable control BE2 T3 O/Z • Decoded from the two lowest bits of the internal address BE1 T2 O/Z • Byte write enables for most types of memory BE0 R2 O/Z • Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF – ADDRESS EA21 L4 EA20 L3 EA19 J2 EA18 J1 EA17 K1 EA16 K2 EA15 L2 EA14 L1 EA13 M1 EA12 M2 O/Z External address (word address) EA11 M6 O/Z External address (word address) EA10 N4 EA9 N1 EA8 N2 EA7 N6 EA6 P4 EA5 P3 EA4 P2 EA3 P1 EA2 P6 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground |
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