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MSP50P34N16I2D Datasheet(PDF) 6 Page - Texas Instruments

Part No. MSP50P34N16I2D
Description  MIXED-SIGNAL PROCESSORS
Download  9 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSP50P34N16I2D Datasheet(HTML) 6 Page - Texas Instruments

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MSP50C32, MSP50C33, MSP50C34
MSP50P34, MSP50C37, MSP50P37
MIXED-SIGNAL PROCESSORS
SPSS019A – MAY 1997 – REVISED OCTOBER 1998
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements
MIN
MAX
UNIT
Initialization
tINIT
INIT pulsed low while the MSP50x3x has power applied (see Figure 1)
1
µs
Wakeup
tsu(wakeup)
Setup time prior to wakeup terminal negative transition (see Figure 2)
1
µs
External Interrupt
t
(i t
t)
Setup time prior to B1 terminal negative transition (see Figure 3)
fclock = 15.36 MHz
1
µs
tsu(interrupt) Setup time prior to B1 terminal negative transition (see Figure 3)
fclock = 19.2 MHz
1.5
µs
Writing (Slave Mode)
tsu1(B1)
Setup time, B1 low before B0 goes low (see Figure 4)
20
ns
tsu(d)
Setup time, data valid before B0 goes high (see Figure 4)
100
ns
th1(B1)
Hold time, B1 low after B0 goes high (see Figure 4)
20
ns
th(d)
Hold time, data valid after B0 goes high (see Figure 4)
30
ns
tw
Pulse duration, B0 low (see Figure 4)
100
ns
tr
Rise time, B0 (see Figure 4)
50
ns
tf
Fall time, B0 (see Figure 4)
50
ns
Reading (Slave Mode)
tsu2(B1)
Setup time, B1 before B0 goes low (see Figure 5)
20
ns
th2(B1)
Hold time, B1 after B0 goes high (see Figure 5)
20
ns
tdis
Output disable time, data valid after B0 goes high (see Figure 5)
0
30
ns
tw
Pulse duration, B0 low (see Figure 5)
100
ns
tr
Rise time, B0 (see Figure 5)
50
ns
tf
Fall time, B0 (see Figure 5)
50
ns
td
Delay time for B0 low to data valid (see Figure 5)
50
ns
PARAMETER MEASUREMENT INFORMATION
tINIT
INIT
Figure 1. Initialization Timing Diagram
tsu(wakeup)
Wakeup
Figure 2. Wakeup Terminal Setup Timing Diagram


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