16-Bit Registered Transceiver

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

SCCS058 - March 1997 - Revised March 2000

CY74FCT163646

Copyright

1CY74FCT163646

Features

• Low power, pin-compatible replacement for LCX and

LPT families

• 5V tolerant inputs and outputs

• 24 mA balanced drive outputs

• Power-off disable outputs permits live insertion

• Edge-rate control circuitry for reduced noise

• FCT-C speed at 5.4 ns

• Latch-up performance exceeds JEDEC standard no. 17

• ESD > 2000V per MIL-STD-883D, Method 3015

• Typical output skew < 250 ps

• Industrial temperature range of –40˚C to +85˚C

• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)

Std 883D

Functional Description

The CY74FCT163646 16-bit transceiver is a three-state,

D-type register, and control circuitry arranged for multiplexed

transmission of data directly from the input bus or from the

internal registers. Data on the A or B bus will be clocked into

the registers as the appropriate clock pin goes to a HIGH logic

level. Output Enable (OE) and direction pins (DIR) are

provided to control the transceiver function. In the transceiver

mode, data present at the high impedance port may be stored

in either the A or B register, or in both. The select controls can

multiplex stored and real-time (transparent mode) data. The

direction control determines which bus will receive data when

the Output Enable (OE) is Active LOW. In the isolation mode

(Output Enable (OE) HIGH), A data may be stored in the B

register and/or B data may be stored in the A register.

The CY74FCT163646 has 24-mA balanced output drivers

with current limiting resistors in the outputs. This reduces the

need for external terminating resistors and provides for

minimal undershoot and reduced ground bounce. The inputs

and outputs were designed to be capable of being driven by

5.0V buses, allowing them to be used in mixed voltage

systems as translators. The outputs are also designed with a

power-off disable feature enabling them to be used in

applications requiring live insertion.

Logic Block Diagrams

C

D

1B1

C

D

1A1

TO 7 OTHER CHANNELS

1SAB

1CLKAB

1CLKBA

1DIR

1SBA

1OE

B REG

A REG

C

D

2B1

C

D

2A1

2SAB

2CLKAB

2CLKBA

2DIR

2SBA

2OE

B REG

TO 7 OTHER CHANNELS

A REG