8-Bit Register

CY54/74FCT273T

SCCS020 - March 1995 - Revised February 2000

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

Copyright

Features

• Function, pinout, and drive compatible with FCT and

F logic

• FCT-C speed at 5.8 ns max. (Com’l)

FCT-A speed at 7.2 ns max. (Com’l)

FCT functions

• Edge-rate control circuitry for significantly improved

noise characteristics

• Power-off disable feature

• Matched rise and fall times

• ESD > 2000V

• Fully compatible with TTL input and output logic levels

• Extended commercial range of

−40˚C to +85˚C

• Sink current

64 mA (Com’l), 32 mA (Mil)

Source current

32 mA (Com’l), 12 mA (Mil)

Functional Description

The FCT273T consists of eight edge-triggered D-type

flip-flops with individual D inputs and Q outputs. The common

buffered clock (CP) and master reset (MR) load and reset all

flip-flops simultaneously. The FCT273T is an edge-triggered

register. The state of each D input (one set-up time before the

LOW-to-HIGH clock transition) is transferred to the corre-

sponding flip-flop’s Q output. All outputs will be forced LOW by

a low voltage level on the MR input.

The outputs are designed with a power-off disable feature to

allow for live insertion of boards.

Note:

1.

H

= HIGH Voltage Level steady state

h

= HIGH Voltage Level one set-up time prior to LOW-to-HIGH clock transition

L

= LOW Voltage Level steady state

l

= LOW Voltage Level one set-up time prior to the LOW-to-HIGH transition

X

= Don’t Care

= LOW-to-HIGH clock transition

Logic Block Diagram

Pin Configurations

FCT273T–1

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

MR

FCT273T–2

4

8

9

10

11

12

76 5

1516 17 18

3

2

1

20

13

14

19

CP

GND

Top View

LCC

MR

1

2

3

4

5

6

7

8

9

10

11

12

16

17

18

19

20

13

14

FCT273T–3

15

Top View

CP

MR

GND

DIP/SOIC/QSOP

FCT273T–4

CP

MR

Logic Symbol

Operating Mode

Inputs

Output

MR

CP

D

Q

Reset (clear)

L

X

X

L

Load ‘1’

H

h

H

Load ‘0’

H

l

L