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CY54FCT841TDIP Datasheet(PDF) 1 Page - Texas Instruments |
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CY54FCT841TDIP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 8 page 10-Bit Latch CY54/74FCT841T SCCS035 - September 1994 - Revised March 2000 Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. Copyright © 2000, Texas Instruments Incorporated Features • Function, pinout, and drive compatible with FCT, F, and AM29841 logic • FCT-C speed at 5.5 ns max. (Com’l) FCT-B speed at 6.5 ns max. (Com’l) • Reduced VOH (typically = 3.3V) versions of equivalent FCT functions • Edge-rate control circuitry for significantly improved noise characteristics • Power-off disable feature • Matched rise and fall times • ESD > 2000V • Fully compatible with TTL input and output logic levels • Sink current 64 mA (Com’l), 32 mA (Mil) Source current 32 mA (Com’l), 12 mA (Mil) • High-speed parallel latches • Buffered common latch enable input Functional Description The FCT841T bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The FCT841T is a buffered 10-bit wide version of the FCT373 function. The FCT841T high-performance interface is designed for high-capacitance load drive capability while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high impedance state and are designed with a power-off disable feature to allow for live insertion of boards. Logic Block Diagram Pin Configurations D Y0 OE D0 LE Q Y1 D1 Y2 D2 Y3 D3 Y4 D4 Y5 D5 YN- 1 DN- 1 YN DN DQ Q DQ Q DQ Q DQ Q DQ Q DQ Q DQ Q LE LE LE LE LE LE LE D Y Q LE D LE OE 10 10 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 24 23 22 21 13 14 VCC 15 DIP/QSOP/SOIC Top View OE D1 D2 D3 D4 D5 D6 D7 D8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 GND D0 D9 Y0 Y9 LE Functional Block Diagram LE |
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