8-Bit Latches

CY54/74FCT373T

CY54/74FCT573T

SCCS021 - May 1994 - Revised February 2000

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

Copyright

Features

• Function and pinout compatible with FCT, and F logic

• FCT-C speed at 4.2 ns max. (Com’l),

FCT-A speed at 5.2 ns max. (Com’l)

FCT functions

• Edge-rate control circuitry for significantly improved

noise characteristics

• Power-off disable feature

• ESD > 2000V

• Matched rise and fall times

• Extended commercial range of

−40˚C to +85˚C

• Fully compatible with TTL input and output logic levels

• Sink current

64 mA (Com’l), 32 mA (Mil)

Source current 32 mA (Com’l), 12 mA (Mil)

Functional Description

The FCT373T and FCT573T consist of eight latches with

three-state outputs for bus organized applications. When latch

enable (LE) is HIGH, the flip-flops appear transparent to the

data. Data that meets the required set-up times are latched

when LE transitions from HIGH to LOW. Data appears on the

bus when the (OE) is LOW. When output enable is HIGH, the

bus output is in the impedance state. In this mode, data may

be entered into the latches. The FCT573T is identical to the

FCT373T except for the flow-through pinout, which simplifies

board design.

The outputs are designed with a power-off disable feature to

allow for live insertion of boards.

Logic Block Diagram

Pin Configurations

1

2

3

4

5

6

7

8

9

10

11

12

16

17

18

19

20

13

14

15

DIP/SOIC/QSOP

Top View

LE

OE

GND

1

2

3

4

5

6

7

8

9

10

11

12

16

17

18

19

20

13

14

15

DIP/SOIC/QSOP

Top View

LE

OE

GND

LE

OE

CP

D

Q

LE

OE

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

FCT373T

FCT573T

Logic Symbol