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CY29FCT52CTSOC Datasheet(PDF) 1 Page - Texas Instruments |
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CY29FCT52CTSOC Datasheet(HTML) 1 Page - Texas Instruments |
1 / 10 page CY29FCT52T 8-BIT REGISTERED TRANSCEIVER SCCS010A – MAY 1994 – REVISED OCTOBER 2001 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Function, Pinout, and Drive Compatible With FCT, F Logic, and AM2952 D Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions D Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D Ioff Supports Partial-Power-Down Mode Operation D Matched Rise and Fall Times D Fully Compatible With TTL Input and Output Logic Levels D 64-mA Output Sink Current 32-mA Output Source Current description The CY29FCT52T has two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and 3-state output-enable signals are provided for each register. Both A outputs and B outputs are specified to sink 64 mA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. PIN DESCRIPTION NAME DESCRIPTION A A register inputs or B register outputs B B register inputs or A register outputs CPA Clock for the A register. When CEA is low, data enters the A register on the low-to-high transition of the CPA signal. CEA Clock enable for the A register. When CEA is low, data enters the A register on the low-to-high transition of the CPA signal. When CEA is high, the A register holds its contents, regardless of CPA signal transitions. OEA Output enable for the A register. When OEA is low, the A register outputs are enabled onto the B lines. When OEA is high, the A outputs are in the high-impedance state. CPB Clock for the B register. When CEB is low, data enters the B register on the low-to-high transition of the CPB signal. CEB Clock enable for the B register. When CEB is low, data enters the B register on the low-to-high transition of the CPB signal. When CEB is high, the B register holds its contents, regardless of CPA signal transitions. OEB Output enable for the B register. When OEB is low, the B register outputs are enabled onto the A lines. When OEB is high, the B outputs are in the high-impedance state. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Q OR SO PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 B7 B6 B5 B4 B3 B2 B1 B0 OEB CPA CEA GND VCC A7 A6 A5 A4 A3 A2 A1 A0 OEA CPB CEB |
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