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CDC516 Datasheet(PDF) 1 Page - Texas Instruments

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Part No. CDC516
Description  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CDC516 Datasheet(HTML) 1 Page - Texas Instruments

 
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CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D Distributes One Clock Input to Four Banks
of Four Outputs
D Separate Output Enable for Each Output
Bank
D External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
D No External RC Network Required
D Operates at 3.3-V VCC
D Packaged in Plastic 48-Pin Thin Shrink
Small-Outline Package
description
The CDC516 is a high-performance, low-skew,
low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both
frequency and phase, the feedback output
(FBOUT) to the clock (CLK) input signal. It is
specifically designed for use with synchronous
DRAMs. The CDC516 operates at 3.3-V VCC and
is designed to drive up to five clock loads per
output.
Four banks of four outputs provide 16 low-skew,
low-jitter copies of the input clock. Output signal
duty
cycles
are
adjusted
to
50
percent,
independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled
separately via the 1G, 2G, 3G, and 4G control
inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the
G inputs are low, the outputs are disabled to the
logic-low state.
Unlike many products containing PLLs, the CDC516 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC516 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL may be bypassed for test purposes by strapping AVCC to ground.
The CDC516 is characterized for operation from 0
°C to 70°C.
Copyright
© 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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VCC
1Y0
1Y1
GND
GND
1Y2
1Y3
VCC
1G
GND
AVCC
CLK
AGND
AGND
GND
2G
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
VCC
4Y0
4Y1
GND
GND
4Y2
4Y3
VCC
4G
GND
AVCC
FBIN
AGND
FBOUT
GND
3G
VCC
3Y0
3Y1
GND
GND
3Y2
3Y3
VCC
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