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CDC516 Datasheet(PDF) 6 Page - Texas Instruments

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Part No. CDC516
Description  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CDC516 Datasheet(HTML) 6 Page - Texas Instruments

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CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
fclock
Clock frequency
25
125
MHz
Input clock duty cycle
40%
60%
Stabilization time†
1
ms
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 30 pF (see Note 5 and Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.165 V
VCC = 3.3 V
± 0.3 V
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
TYP
MAX
tphase error
reference
(see Figure 3)
66 MHz < CLKIN
↑ < 100 MHz
FBIN
–80...400
ps
tphase error, – jitter,
(see Note 6)
CLKIN
↑ = 100 MHz
FBIN
170
360
240
ps
tsk(o)§
Any Y or FBOUT
Any Y or FBOUT
200
ps
Jitter(pk-pk)
F(clkin > 66 MHz)
Any Y or FBOUT
–100
100
ps
Duty cycle
F(clkin
≤ 66 MHz)
Any Y or FBOUT
45%
55%
Duty cycle
F(clkin > 66 MHz)
Any Y or FBOUT
43%
57%
tr
Any Y or FBOUT
1.1
1.5
0.7
1.6
ns
tf
Any Y or FBOUT
0.8
1.3
0.5
1.5
ns
‡ These parameters are not production tested.
§ The tsk(o) specification is only valid for equal loading of all outputs.
NOTES:
5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6. Phase error does not include jitter. The total phase error is 70 ps to 460 ps for the 5% VCC range.


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