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CDC2510C Datasheet(PDF) 3 Page - Texas Instruments

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Part No. CDC2510C
Description  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CDC2510C Datasheet(HTML) 3 Page - Texas Instruments

 
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CDC2510C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS621 – DECEMBER 1998
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
TYPE
DESCRIPTION
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the CDC2510C clock driver. CLK is
used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK
must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock
the feedback signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
G
11
I
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-
Ω series-damping resistor.
1Y (0:9)
3, 4, 5, 8, 9
15, 16, 17, 20,
21
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
Each output has an integrated 25-
Ω series-damping resistor.
AVCC
23
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs.
AGND
1
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
2, 10, 14, 22
Power
Power supply
GND
6, 7, 18, 19
Ground
Ground


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