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CDC2510C Datasheet(PDF) 4 Page - Texas Instruments

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Part No. CDC2510C
Description  3.3-V PHASE-LOCK LOOP CLOCK DRIVER
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CDC2510C Datasheet(HTML) 4 Page - Texas Instruments

 
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CDC2510C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS621 – DECEMBER 1998
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, AVCC (see Note 1)
AVCC < VCC +0.7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, VCC, AVCC
–0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 2)
–0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high
or low state, VO (see Notes 2 and 3)
–0.5 V to VCC + 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0)
–50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC)
±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC)
±50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND
±100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 4)
0.7 W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
–65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. AVCC must not exceed VCC.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The maximum package power dissipation is calculated using a junction temperature of 150
°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
recommended operating conditions (see Note 5)
MIN
MAX
UNIT
VCC, AVCC Supply voltage
3
3.6
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
IOH
High-level output current
–12
mA
IOL
Low-level output current
12
mA
TA
Operating free-air temperature
0
85
°C
NOTE 5: Unused inputs must be held high or low to prevent them from floating.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
fclk
Clock frequency
25
125
MHz
Input clock duty cycle
40%
60%
Stabilization time†
1
ms
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.


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