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CD74HC4015 Datasheet(PDF) 4 Page - Texas Instruments

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Part No. CD74HC4015
Description  High Speed CMOS Logic Dual 4-Stage Static Shift Register
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD74HC4015 Datasheet(HTML) 4 Page - Texas Instruments

   
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4
Prerequisite for Switching Specifications
PARAMETER
SYMBOL
VCC (V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
Maximum Clock
Frequency
fMAX
2
6
-5-4-
MHz
4.5
30
-
24
-
20
-
MHz
6
35
-
28
-
24
-
MHz
Clock Pulse Width
tW
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14-17
-20-
ns
MR Pulse Width
tW
2
150
-
190
-
225
-
ns
4.5
30
-
38
-
45
-
ns
6
26-33
-38-
ns
MR Recovery Time
tREC
2
50-65
-75-
ns
4.5
10
-
13
-
15
-
ns
6
9
-
11
-
13
-
ns
Set-up Time,
Data-In to CP
tSUL, tSUH
2
60-75
-90-
ns
4.5
12
-
15
-
18
-
ns
6
10-13
-15-
ns
Hold Time,
Data-In to CP
tH
2
0
-0-0-
ns
4.5
0
-
0
-
0
-
ns
6
0
-0-0-
ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC
(V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Propagation Delay (Figure 1)
tPLH,
tPHL
CL = 50pF
2
-
-
175
-
220
-
270
ns
Clock to Qn
4.5
-
-
35
-
44
-
54
ns
CL =15pF
5
-
14
-
-
-
-
-
ns
CL = 50pF
6
-
-
30
-
37
-
46
ns
MR to Qn, (Clock High)
tPLH,
tPHL
CL = 50pF
2
-
-
275
-
345
-
415
ns
4.5
-
-
55
-
64
-
83
ns
CL =15pF
25
-
-
-
-
-
ns
CL = 50pF
6
-
-
47
-
54
-
71
ns
MR to Qn, (Clock Low)
tPLH,
tPHL
CL = 50pF
2
-
-
325
-
400
-
490
ns
4.5
-
-
65
-
81
-
98
ns
CL =15pF
25
-
-
-
-
-
ns
CL = 50pF
6
-
-
55
-
69
-
83
ns
Output Transition Time
(Figure 1)
tTLH,tTHL CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
Maximum Clock Frequency
fMAX
CL =15pF
5
-
60
-
-
-
-
-
MHz
Power Dissipation
Capacitance
(Notes 4, 5)
CPD
CL =15pF
5
-
43
-
-
-
-
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per shift register.
5. PD = VCC
2 f
i + ∑ CL VCC
2 where f
i = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CD74HC4015


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