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CD74HC240 Datasheet(PDF) 6 Page - Texas Instruments

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Part No. CD74HC240
Description  High Speed CMOS Logic Octal Buffer/Line Drivers, Three-State
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD74HC240 Datasheet(HTML) 6 Page - Texas Instruments

   
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6
Output Enable and Disable
Times
tTLH, tTHL
CL = 50pF
4.5
-
-
30
-
-
38
-
-
45
ns
Output Transition Time
tTHL, tTLH
CL = 50pF
4.5
-
-
12
-
-
15
-
-
18
ns
Input Capacitance
CI
CL = 50pF
-
10
-
10
-
-
10
-
-
10
pF
Power Dissipation Capacitance
(Notes 5, 6))
CPD
HCT240
-
5
-
40
-
-
-
----
pF
HCT241
-
5
-
38
-
-
-
----
pF
HCT244
-
5
-
40
-
-
-
----
pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per channel.
6. PD = VCC
2 f
i (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDI-
TIONS
VCC
(V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Test Circuits and Waveforms
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
tPHL
tPLH
tTHL
tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns
tf = 6ns
90%
tPHL
tPLH
tTHL
tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns
tf = 6ns
90%
50%
10%
90%
GND
VCC
10%
90%
50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
6ns
6ns
tPZH
tPHZ
tPZL
tPLZ
0.3
2.7
GND
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
tr
6ns
tPZH
tPHZ
tPZL
tPLZ
6ns
tf
1.3
CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244


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