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CD74HC173 Datasheet(PDF) 6 Page - Texas Instruments

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Part No. CD74HC173
Description  High Speed CMOS Logic Quad D-Type Flip-Flop, Three-State
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD74HC173 Datasheet(HTML) 6 Page - Texas Instruments

 
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6
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC (V)
25oC
-40oC TO 85oC
-55oCTO125oC
UNITS
TYP
MAX
MAX
MAX
HC TYPES
Propagation Delay, Clock to
Output
tPLH, tPHL
CL = 50pF
2
-
200
250
300
ns
4.5
-
40
50
60
ns
CL = 15pF
5
17
-
-
-
ns
CL = 50pF
6
-
34
43
51
ns
Propagation Delay, MR to
Output
tPHL
CL = 50pF
2
-
175
220
265
ns
4.5
-
35
44
53
ns
CL = 15pF
5
12
-
-
-
ns
CL = 50pF
6
-
30
37
45
ns
Propagation Delay Output
Enable to Q (Figure 6)
tPLZ, tPHZ
tPZL, tPZH
CL = 50pF
2
150
190
225
ns
CL = 50pF
4.5
30
38
45
ns
CL = 15pF
5
12
-
-
-
ns
CL = 50pF
6
26
33
38
ns
Output Transition Times
tTLH, tTHL
CL = 50pF
2
-
60
75
90
ns
4.5
-
12
15
18
ns
6
-
10
13
15
ns
Maximum Clock Frequency
fMAX
CL = 15pF
5
60
-
-
-
MHz
Input Capacitance
CIN
--
-
10
10
10
pF
Three-State Output
Capacitance
CO
--
-
10
10
10
pF
Power Dissipation
Capacitance
(Notes 5, 6)
CPD
-
5
29
-
-
-
pF
HCT TYPES
Propagation Delay, Clock to
Output
tPLH, tPHL
CL = 50pF
4.5
-
40
50
60
ns
CL = 15pF
5
17
-
-
-
ns
Propagation Delay, MR to
Output
tPHL
CL = 50pF
4.5
-
44
55
66
ns
CL = 15pF
5
18
-
-
-
ns
Propagation Delay Output
Enable to Q (Figure 6)
tPZL, tPZH
CL = 50pF
2
150
190
225
ns
CL = 50pF
4.5
30
38
45
ns
CL = 15pF
5
14
-
-
-
ns
CL = 50pF
6
26
33
38
ns
Output Transition Times
tTLH, tTHL
CL = 50pF
4.5
-
15
19
22
ns
Maximum Clock Frequency
fMAX
CL = 15pF
5
60
-
-
-
MHz
Input Capacitance
CIN
--
-
10
10
10
pF
Power Dissipation
Capacitance
(Notes 5, 6)
CPD
-
5
34
-
-
-
pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per package.
6. PD =VCC
2 f
i + ∑ (CL VCC
2 +f
O) where fi = Input Frequency, fO = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CD74HC173, CD74HCT173


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