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CD74HC166 Datasheet(PDF) 6 Page - Texas Instruments

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Part No. CD74HC166
Description  High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD74HC166 Datasheet(HTML) 6 Page - Texas Instruments

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6
Output Transition Time
(Figure 3)
tTLH, tTHL
CL = 50pF
2
-
75
95
110
ns
4.5
-
15
19
22
ns
6
-
13
16
19
ns
Propagation Delay
MR to Output
(Figure 3)
tPHL
CL = 50pF
2
-
160
200
240
ns
4.5
-
32
40
48
ns
6
-
27
34
41
ns
Input Capacitance
CI
--
-
10
10
10
pF
Power Dissipation
Capacitance
(Notes 3, 4)
CPD
-
5
41
-
-
-
pF
HCT TYPES
Propagation Delay,
Clock to Output
(Figure 4)
tPLH, tPHL
CL = 50pF
4.5
-
40
50
60
ns
Output Transition Time
(Figure 4)
tTLH, tTHL
CL = 50pF
4.5
-
15
19
22
ns
Propagation Delay
MR to Output (Figure 4)
tPHL
CL = 50pF
4.5
-
40
50
60
ns
Input Capacitance
CI
--
-
10
10
10
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD= CPD VCC
2f
i + ∑ (CL VCC
2 +f
O) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC (V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
TYP
MAX
MAX
MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
CLOCK
90%
50%
10%
GND
VCC
trCL
tfCL
50%
50%
tWL
tWH
10%
tWL + tWH =
fCL
I
CLOCK
2.7V
1.3V
0.3V
GND
3V
trCL = 6ns
tfCL = 6ns
1.3V
1.3V
tWL
tWH
0.3V
tWL + tWH =
fCL
I
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166


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