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CD74HC138 Datasheet(PDF) 1 Page - Texas Instruments

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Part No. CD74HC138
Description  High Speed CMOS Logic 3-to-8 Line Decoder/ Demultiplexer Inverting and Non-Inverting
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD74HC138 Datasheet(HTML) 1 Page - Texas Instruments

   
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1
Data sheet acquired from Harris Semiconductor
SCHS147A
Features
• Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
• l/O Port or Memory Selector
• Three Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13ns at VCC = 5V,
CL = 15pF, TA = 25
oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Pinout
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
(PDIP, SOIC)
TOP VIEW
Signal names in parentheses are for ’HC238 and ’HCT238.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A0
A1
A2
E1
E2
E3
GND
(Y7) Y7
VCC
Y1 (Y1)
Y2 (Y2)
Y3 (Y3)
Y4 (Y4)
Y5 (Y5)
Y6 (Y6)
Y0 (Y0)
October 1997 - Revised February 1999
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 1999, Texas Instruments Incorporated
CD74HC138, CD74HCT138,
CD74HC238, CD74HCT238
High Speed CMOS Logic 3-to-8 Line Decoder/
Demultiplexer Inverting and Non-Inverting
[ /Title
(CD74
HC138
,
CD74
HCT13
8,
CD74
HC238
,
CD74
HCT23
8)
/Sub-
ject
(High
Speed


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