CD74HC02 datasheet(5/6 Pages) TI | High Speed CMOS Logic Quad Two-Input NOR Gate

Part No.	CD74HC02

Description	High Speed CMOS Logic Quad Two-Input NOR Gate

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Maker	TI [Texas Instruments]

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Power Dissipation Capacitance

(Notes 4, 5)

CPD

-5

HCT TYPES

Propagation Delay, Input to

Output (Figure 2)

tPLH, tPHL

CL = 50pF

4.5

Propagation Delay, Data Input

to Output Y

tPLH, tPHL

CL = 15pF

Transition Times (Figure 2)

tTLH, tTHL

CL = 50pF

4.5

Input Capacitance

CIN

Power Dissipation Capacitance

(Notes 4, 5)

CPD

-5

NOTES:

4. CPD is used to determine the dynamic power consumption, per gate.

5. PD = VCC

2 f

i (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

VCC (V)

25oC

-40oC TO

85oC

-55oC TO

125oC

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Test Circuits and Waveforms

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL

tPLH

tTHL

tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns

tf = 6ns

90%

tPHL

tPLH

tTHL

tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns

tf = 6ns

90%

CD74HC02, CD74HCT02

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CD74HC02 Datasheet(PDF) 5 Page - Texas Instruments

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