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CD74AC74 Datasheet(PDF) 1 Page - Texas Instruments

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Part No. CD74AC74
Description  Dual D-Type Flip-Flop with Set and Reset Positive-Edge-Triggered
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD74AC74 Datasheet(HTML) 1 Page - Texas Instruments

   
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1
Data sheet acquired from Harris Semiconductor
SCHS231
Features
• Buffered Inputs
• Typical Propagation Delay (AC00)
- 4.9ns at VCC = 5V, TA = 25
oC, C
L = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Lachup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50
Ω Transmission Lines
Description
The Harris CD74AC74 and CD74ACT74 dual D-type, posi-
tive edge triggered flip-flops use the Harris ADVANCED
CMOS technology. These flip-flops have independent DATA,
SET, RESET, and CLOCK inputs and Q and Q outputs. The
logic level present at the data input is transferred to the out-
put during the positive going transition of the clock pulse.
SET and RESET are independent of the clock and are
accomplished by a low level at the appropriate input.
Pinout
CD74AC74, CD74ACT74
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
CD74AC74E
0 to 70, -40 to 85
-55 to 125
14 Ld PDIP
E14.3
CD74ACT74E
0 to 70, -40 to 85
-55 to 125
14 Ld PDIP
E14.3
CD74AC74EX
0 to 70, -40 to 85
-55 to 125
14 Ld PDIP
E14.3
CD74ACT74EX
0 to 70, -40 to 85
-55 to 125
14 Ld PDIP
E14.3
CD74AC74M
0 to 70, -40 to 85
-55 to 125
14 Ld SOIC
M14.15
CD74ACT74M
0 to 70, -40 to 85
-55 to 125
14 Ld SOIC
M14.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
1R
1D
1CP
1S
1Q
1Q
GND
VCC
2R
2D
2CP
2S
2Q
2Q
1
2
3
4
5
6
7
14
13
12
11
10
9
8
September 1998
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright
© Harris Corporation 1998
CD74AC74,
CD74ACT74
Dual D-Type Flip-Flop with Set and Reset
Positive-Edge-Triggered
File Number
1881.1
[ /Title
(CD74
AC74,
CD74
ACT74
)
/Sub-
ject
(Dual
D-
Type
Flip-
Flop
with
Set and
Reset
Posi-
tive-
Edge-
Trig-
gered)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Advan
ced
CMOS
, Harris
Semi-
con-
ductor,
Advan


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