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CD74AC74 Datasheet(PDF) 6 Page - Texas Instruments

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Part No. CD74AC74
Description  Dual D-Type Flip-Flop with Set and Reset Positive-Edge-Triggered
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CD74AC74 Datasheet(HTML) 6 Page - Texas Instruments

   
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6
Propagation Delay, R, StoQ, QtPLH
1.5
-
-
120
-
-
132
ns
3.3
3.8
-
13.4
3.7
-
14.7
ns
5
2.7
-
9.5
2.6
-
10.5
ns
tPHL
1.5
-
-
131
-
-
144
ns
3.3
4.1
-
14.6
4
-
16.1
ns
5
3
-
10.4
2.9
-
11.5
ns
Input Capacitance
CI
-
-
-10-
-10
pF
Power Dissipation Capacitance
CPD
(Note 16)
-
-
55
-
-
55
-
pF
ACT TYPES
Propagation Delay, CP to Q, QtPHL
tPLH
5
(Note 15)
2.5
-
8.6
2.4
-
9.5
ns
Propagation Delay, R, StoQ, QtPLH
5
3
-
10.5
2.9
-
11.5
ns
tPHL
5
3.2
-
11.4
3.1
-
12.5
ns
Input Capacitance
CI
-
-
-10-
-10
pF
Power Dissipation Capacitance
CPD
(Note 16)
-
-
55
-
-
55
-
pF
NOTES:
13. Limits tested 100%.
14. 3.3V Min at 3.6V, Max at 3V.
15. 5V Min at 5.5V, Max at 4.5V.
16. CPD is used to determine the dynamic power consumption per flip-flop.
PD =CPDVCC
2 f
i + Σ (CLVCC
2 f
o)+VCC ∆ICC where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC =
supply voltage.
FIGURE 1.
FIGURE 2.
FIGURE 3.
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) (Continued)
PARAMETER
SYMBOL
VCC (V)
-40oC TO 85oC
-55oC TO 125oC
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
INPUT LEVEL
CP
GND
Q OR Q
VS
tW
tPHL
tPLH
VS
VS
VS
VS
INPUT LEVEL
GND
INPUT
CP
R (S)
VS
tW
tREM
tPLH
Q
(Q)
Q
(Q)
VS
VS
VS
INPUT LEVEL
GND
D
CP
VS
tSU(L)
tH(L)
tH(H)
tSU(H)
VS
VS
VS
VS
VS
INPUT LEVEL
GND
CD74AC74, CD74ACT74


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