CD74ACT174 datasheet(6/7 Pages) TI

Part #	CD74ACT174

Description	Hex D Flip-Flop with Reset

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6

Propagation Delay, MR to Qn

tPLH, tPHL

1.5

-

165

-

181

ns

3.3

5.2

-

18.5

5.1

-

20.3

ns

5

3.7

-

13.2

3.6

-

14.5

ns

Input Capacitance

CI

-

-10-

-10

pF

Power Dissipation Capacitance

CPD

(Note 11)

-

37

-

37

-

pF

ACT TYPES

Propagation Delay, CP to Qn

tPLH, tPHL

5

(Note 10)

3.6

-

12.6

3.5

-

14

ns

Propagation Delay, MR to Qn

tPLH, tPHL

5

4

-

14.1

3.9

-

15.5

ns

Input Capacitance

CI

-

-10-

-10

pF

Power Dissipation Capacitance

CPD

(Note 11)

-

37

-

37

-

pF

NOTES:

8. Limits tested 100%.

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V.

11. CPD is used to determine the dynamic power consumption per flip-flop.

PD =CPD VCC

2 f

i + Σ (CL +VCC2fo)+VCC ∆ICC where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC =

supply voltage.

Switching Speciﬁcations Input tr, tf = 3ns, CL = 50pF (Worst Case) (Continued)

PARAMETER

SYMBOL

VCC (V)

-40oC TO 85oC

-55oC TO 125oC

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

FIGURE 1. PROPAGATION DELAYS

FIGURE 2. RESET OR SET PREREQUISITE AND

PROPAGATION DELAYS

INPUT LEVEL

CP

GND

VS

tW

tPHL

tPLH

VS

INPUT LEVEL

GND

INPUT

CP

MR

VS

tW

tREM

tPHL

Q

(Q)

VS

FIGURE 3.

INPUT LEVEL

GND

D

CP

VS

tSU(L)

tH(L)

tH(H)

tSU(H)

VS

INPUT LEVEL

GND

DUT

OUTPUT

RL (NOTE)

OUTPUT

LOAD

500

Ω

CL

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

FIGURE 4. PROPAGATION DELAY TIMES

AC

ACT

Input Level

VCC

3V

Input Switching Voltage, VS

0.5 VCC

1.5V

Output Switching Voltage, VS

0.5 VCC

CD74AC174, CD54/74ACT174

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CD74ACT174 Datasheet(PDF) 6 Page - Texas Instruments

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