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S25FL032P Datasheet(PDF) 25 Page - SPANSION |
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S25FL032P Datasheet(HTML) 25 Page - SPANSION |
25 / 64 page February 12, 2009 S25FL032P_00_02 S25FL032P 25 Data Sheet (Preliminar y ) 9.3 Dual Output Read Mode (DOR) The Dual Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out 2 bits at a time using 2 pins (SI/IO0 and SO/IO1) instead of 1 bit, at a maximum frequency of 80 MHz. The Dual Output Read mode effectively doubles the data transfer rate compared to the FAST_READ instruction. The host system must first select the device by driving CS# low. The Dual Output Read command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. Then the memory contents, at the address that is given, are shifted out two bits at a time through the IO0 (SI) & IO1 (SO) pins at a frequency fSCK on the falling edge of SCK. The Dual Output Read command sequence is shown in Figure 9.3 and Table 9.1 on page 22. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single Dual Output Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. The Dual Output Read command is terminated by driving CS# high at any time during data output. The device rejects any Dual Output Read command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. Figure 9.3 Dual Output Read Instruction Sequence CS# SCK SO/IO1 SI Switches from Input to Output 24 Bit Address Dummy Byte Hi-Z Byte 2 *MSB 28 29 30 31 32 33 34 35 36 37 38 3940414243 44 45 46 47 23 * 22 21 3 2107 * 654 3 210 6420 SI/IO0 012 3 4 56 7 8 9 10 Instruction Byte 1 7 5 3 1 7 * 5 3 1 7 * 6420 6 |
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