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S25FL032P Datasheet(PDF) 26 Page - SPANSION |
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S25FL032P Datasheet(HTML) 26 Page - SPANSION |
26 / 64 page 26 S25FL032P S25FL032P_00_02 February 12, 2009 D a ta Sheet (Prel i m i nar y) 9.4 Quad Output Read Mode (QOR) The Quad Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out 4 bits at a time using 4 pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3) instead of 1 bit, at a maximum frequency of 80 MHz. The Quad Output Read mode effectively doubles the data transfer rate compared to the Dual Output Read instruction, and is four times the data transfer rate of the FAST_READ instruction. The host system must first select the device by driving CS# low. The Quad Output Read command is then written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge of SCK. Then the memory contents, at the address that are given, are shifted out four bits at a time through IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#) pins at a frequency fSCK on the falling edge of SCK. The Quad Output Read command sequence is shown in Figure 9.4 and Table 9.1 on page 22. The first address byte specified can start at any location of the memory array. The device automatically increments to the next higher address after each byte of data is output. The entire memory array can therefore be read with a single Quad Output Read command. When the highest address is reached, the address counter reverts to 00000h, allowing the read sequence to continue indefinitely. The Quad Output Read command is terminated by driving CS# high at any time during data output. The device rejects any Quad Output Read command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. The Quad bit of Configuration Register must be set (CR Bit1 = 1) to enable the Quad mode capability of the S25FL device. Figure 9.4 Quad Output Read Instruction Sequence CS# SCK SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 SI Switches from Input to Output 24 Bit Address Dummy Byte Hi-Z *MSB 28 29 30 31 32 33 34 35 36 37 38 3940414243 44 45 46 47 23 * 22 21 3 2 107 6 5 4 3 2 * 10 4 012 3 4567 8 910 Instruction 51 7 * 5 3 4 2 0 6 Hi-Z Hi-Z DATA OUT 1 DATA OUT 2 DATA OUT 3 DATA OUT 4 7 * 3 7 * 3 7 * 3 7 * 2 6 2 6 2 6 6 51 51 51 4 0 4 0 4 0 |
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