Gain Amplifier

D83S Series

Digital Programming & Control

1784 Chessie Lane, Ottawa, IL 61350 • Tel: 800/252-7074, 815/434-7800 • FAX: 815/434-8176

e-mail: sales@freqdev.com • Web Address: http://www.freqdev.com

The Clock shifts the input data Di through the shift registers when it transitions from low to high. For the

input data to be accurately received, it must have been present for at least Ts at the time of the rising

clock transition. The maximum clock pulse frequency is 1.25MHz.

Data from the shift registers propagates through the latches when the strobe is high. Data is latched

when the Strobe transitions from high to low. To retain a programmed setting it is necessary to hold the

strobe low (or to shut off the clock). Keeping the strobe low will allow the clock to shift a new set of input

data into the registers without changing the latched setting.

To latch a new set of data the strobe must be set to its high state, after the last bit of the new input word

(D0) has been shifted in (>Tcs), held high for a minimum time of Tsw and then returned to its low state to

latch and hold the setting. The return of S to its low state must occur before the rise of the clock that

accepts the D7 of the next data word (Tsc>0).

Notes:

1.)

Data is shifted into register on positive edge of clock.

2.)

Data is latched on negative edge of strobe.

3.)

Ts is set up time (valid data before clock).

4.)

Tcs is time between D0 clock and start of strobe.

5.)

Tsw is strobe width.

6.)

Tsc is time between strobe end and D7 clock (next word).

7.)

Tcw is clock width.

8.)

Th is hold time (Valid data after clock rising edge).

Minimum Setup Times

Ts

>125nS

Time data must be present before rise of clock pulse.

Tcs

>260nS

Time from rise of Clock for last data bit, D0, to rise of Strobe pulse.

Tsw

>200nS

Strobe width.

Tsc

>0nS

Time from fall of Strobe to rise of next Clock pulse.

Tcw

>200nS

Clock pulse width.

Cf

1.25 MHz

Maximum Clock pulse frequency.

Th

>5nS

Time data must be valid after rise of clock pulse.

Caution!!

Note 1: The C, P and Di inputs are Tri-state C-MOS logic. They contain protection circuitry to guard against damage due to high static voltages or

electric fields, however the application of any voltages higher than the +5V or lower than the 0V supply voltages can cause permanent damage.

These inputs must always be connected to an appropriate logic voltage level. Permanent damage can also result if C, P and Di are allowed to float

unconnected. If the D83S is used in a configuration where these inputs can become disconnected from their drive circuits, or if their drive circuits

are not powered by the same +5V source, it is recommended to use 10k

Ω pull up resistors to +5V on these inputs.

=Don't care

Strobe

Data

D7

Valid Input

D6

Valid Input

D0

Valid Input

D7

Valid Input

Ts

Tcw

Tcs

Tsc

Clock

Tsw

Th > 5ns

Timing Diagram

3