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D83S-D Datasheet(PDF) 2 Page - Frequency Devices, Inc. |
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D83S-D Datasheet(HTML) 2 Page - Frequency Devices, Inc. |
2 / 4 page Gain Amplifier D83S Series Digital Programming & Control 1784 Chessie Lane, Ottawa, IL 61350 • Tel: 800/252-7074, 815/434-7800 • FAX: 815/434-8176 e-mail: sales@freqdev.com • Web Address: http://www.freqdev.com The D83S programs via a three terminal serial data interface over a gain range from 0.25 (~-12dB) to 1024 (~+60dB) using Clock (C), Strobe (S) and Data inputs (Di). A Data out (Do) connection is provided to permit cascading of multiple D83S’s or “looping” of the input data to verify the programmed setting. Two stages of programmable gain/attenuation are used to optimize the D-C offset and gain bandwidth performance. The gain programming equation is: G=[1+3xD0+12xD1+48xD2+64xD3]x[1/4+(1/4)xD4+(1/2)xD5+D6]x[1+3xD7] where D0 - D7 = “0” or “1” Note: the use of the compliments of D0, D1, D2 and D3. C, S and Di Input Specifications Input Data Levels (Cmos/TTL Logic) Input Voltage (Vd = 5Vdc) Low Level In 0 Vdc min., 1.5 Vdc max. High Level In 3.5 Vdc min., 5.0 Vdc max. Input Current Low Level In -10-5 µA typ., -1 µA max. High Level In +10-5 µA typ., +1 µA max. Input Capacitance 5 pF typ., 7.5 pF max. Recommended Programming Table All combinations of programming inputs produce valid gain settings as determined by the gain equation but can result in unusual values of gain. To minimize the multiplication of D-C offset and to maximize the bandwidth at high gains the following is the recommended programming format for binary weighted gains from 1/4 (~-12dB) to 1024 (~60dB). Gain ( V/V ) Gain (~dB) D0 D1 D2 D3 D4 D5 D6 D7 1/4 -12.04 11110000 1/2 -6.02 11111000 10.00 11111100 2 +6.02 11111110 4 +12.04 01111100 8 +18.06 01111110 16 +24.08 00111100 32 +30.10 00111110 64 +36.12 00011100 128 +42.14 00001100 256 +48.16 00001110 512 +54.19 00001101 1024 +60.21 00001111 Programming Sequence The programming input circuit is a CD4094 series 8 bit shift register with latches. It requires an 8 bit input serial data stream, Di (D0 to D7), a clock C to shift and a strobe S to latch the data (see note 1). A timing sequence must be observed to insure accurate shifting and latching of the input data. The input data bits, D0 through D7 are entered in reverse order, i.e. the MSB, D7, is the first bit to be entered followed by D6 etc. and ending with the LSB, D0 (refer to timing diagram). 2 |
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