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BQ4845YS- Datasheet(PDF) 16 Page - Texas Instruments |
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BQ4845YS- Datasheet(HTML) 16 Page - Texas Instruments |
16 / 22 page 16 Power-Down/Power-Up Timing (TA =TOPR) Symbol Parameter Minimum Typical Maximum Unit Conditions tF VCC slew from 4.75 to 4.25V 300 - - µs tFS VCC slew from 4.25 to VSO 10 - - µs tR VCC slew from VSO to VPFD(MAX) 100 - - µs tPF Interrupt delay from VPFD 6- 24 µs tWPT Write-protect time for external RAM 90 100 125 µs Delay after VCC slews down past VPFD before SRAM is write-protected and RST activated. tCSR CS at VIH after power-up 100 200 300 ms Internal write-protection period af- ter VCC passes VPFD on power-up. tRST VPFD to RST inactive tCSR -tCSR ms Reset active time-out period tCER Chip enable recovery time tCSR -tCSR ms Time during which external SRAM is write-protected after VCC passes VPFD on power-up. tCED Chip enable propagation delay to external SRAM - 9 12 ns Output load A Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity. Aug. 1995 Power-Down/Power-Up Timing Notes: PWRIE set to “1” to enable power fail interrupt. RST and INT are open drain and require an external pull-up resistor. bq4845/bq4845Y |
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