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BQ4845YP- Datasheet(PDF) 1 Page - Texas Instruments |
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BQ4845YP- Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 22 page  Features ® Real-Time Clock counts seconds through years in BCD format ® On-chip battery-backup switchover circuit with nonvolatile control for external SRAM ® Less than 500nA of clock opera- tion current in backup mode ® Microprocessor reset valid to VCC =VSS ® Independent watchdog timer with a programmable time-out period ® Power-fail interrupt warning ® Programmable clock alarm inter- rupt active in battery-backup mode ® Programmable periodic interrupt ® Battery-low warning General Description The bq4845 Real-Time Clock is a low-power microprocessor periph- eral that integrates a time-of-day clock, a 100-year calendar, and a CPU supervisor in a 28-pin SOIC or DIP. The bq4845 is ideal for fax ma- chines, copiers, industrial control systems, point-of-sale terminals, data loggers, and computers. The bq4845 provides direct connec- tions for a 32.768KHz quartz crystal and a 3V backup battery. Through the use of the conditional chip en- able output (CEOUT) and battery voltage output (VOUT) pins, the bq4845 can write-protect and make nonvolatile external SRAMs. The backup cell powers the real-time clock and maintains SRAM infor- mation in the absence of system voltage. The bq4845 contains a temperature- compensated reference and comparator circuit that monitors the status of its voltage supply. When the bq4845 de- tects an out-of-tolerance condition, it generates an interrupt warning and subsequently a microprocessor reset. The reset stays active for 200ms after VCC rises within tolerance, to allow for power supply and processor stabiliza- tion. The bq4845 also has a built-in watchdog timer to monitor processor operation. If the microprocessor does not toggle the watchdog input (WDI) within the programmed time-out pe- riod, the bq4845 asserts WDO and RST. WDI unconnected disables the watchdog timer. The bq4845 can generate other in- terrupts based on a clock alarm con- dition or a periodic setting. The alarm interrupt can be set to occur from once per second to once per month. The alarm can be made active in the battery-backup mode to serve as a system wake-up call. For inter- rupts at a rate beyond once per sec- ond, the periodic interrupt can be pro- grammed with periods of 30.5 µsto 500ms. 1 Aug. 1995 1 PN484501.eps 28-DIP or SOIC 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 9 10 20 19 11 12 18 17 13 14 VCC WE CEIN CEOUT BC WDI OE CS VSS DQ7 DQ8 DQ5 DQ4 DQ3 16 15 VOUT X1 X2 WDO INT RST A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Pin Connections A0–A3 Clock/control address inputs DQ0–DQ7 Data inputs/outputs WE Write enable OE Output enable CS Chip select input CEIN External RAM chip enable CEOUT Conditional RAM chip enable X1–X2 Crystal inputs Pin Names BC Backup battery input VOUT Back-up battery output INT Interrupt output RST Microprocessor reset WDI Watchdog input WDO Watchdog output VCC +5V supply VSS Ground bq4845/bq4845Y Parallel RTC With CPU Supervisor |
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