LOGIC Devices Incorporated

www.logicdevices.com

January 23, 2008 LDS-44xx-A

High Performance Memory Product

16

MEMORY

FRAME

Video Memory / FIFO

LF4460

LF4430

LF4415

PRELIMINARY

RESET RCLK REN RCLR RSET RDWRB ADDR PrevAdd IntAdd Description

Master reset - write/read pointers are clearedMaster reset

REN pipelined by 1 RCLK cycle

Increment read pointer - read from addr 1

Halt read pointer - no output register update- no read operation

Increment read pointer - read from addr 2

Override read pointer to Ext. Addr. Port - read from addr. An

Override read pointer to Ext. Addr. Port - read from addr. Am

Increment read pointer - read from addr Am+1

Clear read pointer - read from addr 0

Increment read pointer - read from addr 1

0

1

1

1

1

1

1

1

1

1

X

1

1

1

1

0

0

1

1

1

X

X

X

X

X

1

1

X

X

X

X

X

X

X

X

An

Am

X

X

X

X

0

1

0

0

0

0

0

0

--

X

1

1

1

1

1

1

1

0

1

Figure 8 - Read Address Pointer Control

X

0000

0000

0001

0001

0002

An

Am

Am+1

0000

0000

0000

0001

0001

0002

An

Am

Am+1

0000

1

Address Control

1. Overriding the Read address is only possible in Single-Channel modes. Holding RSET LOW for multiple cycles allows multi-cycle or ‘full-time’ Read address override

- with the address capable of changing every cycle

2. An additional 8 rising RCLK edges are required for the Memory contents to appear on Qx[11:0]

[1]

NOTES:

[2]