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LTC4217CFE Datasheet(PDF) 10 Page - Linear Technology |
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LTC4217CFE Datasheet(HTML) 10 Page - Linear Technology |
10 / 18 page LTC4217 10 4217fc APPLICATIONS INFORMATION evident from this graph that the power dissipation at 12V, 300mA for 40ms is in the safe region. Adding a capacitor and a 1k series resistor from GATE to ground will lower the inrush current below the default value set by the INRUSH circuit. The GATE is charged with an 24μA current source (when INRUSH circuit is not driving the GATE). The voltage at the GATE pin rises with a slope equal to 24μA/CGATE and the supply inrush current is set at: IINRUSH = CL CGATE •24µA When the GATE voltage reaches the MOSFET threshold voltage, the switch begins to turn on and the OUT volt- age follows the GATE voltage as it increases. Once OUT reaches VDD, the GATE will ramp up until clamped by the 6.15V Zener between GATE and OUT. As the OUT voltage rises, so will the FB pin which is moni- toring it. Once the FB pin crosses its 1.235V threshold and the GATE to OUT voltage exceeds 4.2V, the PG pin will cease to pull low and indicate that the power is good. Parasitic MOSFET Oscillation When the N-channel MOSFET ramps up the output dur- ing power-up it operates as a source follower. The source follower configuration may self-oscillate in the range of 25kHz to 300kHz when the load capacitance is less than 10μF, especially if the wiring inductance from the supply to the VDD pin is greater than 3μH. The possibility of oscil- lation will increase as the load current (during power-up) increases. There are two ways to prevent this type of oscillation. The simplest way is to avoid load capacitances below 10μF. For wiring inductance larger than 20μH, the minimum load capacitance may extend to 100μF. A second choice is to connect an external gate capacitor CP >1.5nF as shown in Figure 3. Turn-Off Sequence The switch can be turned off by a variety of conditions. A normal turn-off is initiated by the UV pin going below its 1.235V threshold. Additionally, several fault conditions will turn off the switch. These include an input overvoltage Figure 2. Supply Turn-On Figure 1. 0.8A, 12V Card Resident Application After the power-on-reset pulse, the LTC4217 will go through the following sequence. First, the UV and OV pins must indicate that the input voltage is within the acceptable range. All of these conditions must be satisfied for the duration of 100ms to ensure that any contact bounce during the insertion has ended. The MOSFET is turned on by charging up the GATE with a charge pump generated current source whose value is ad- justed by shunting a portion of the pull-up current to ground. The charging current is controlled by the INRUSH circuit that maintains a constant slope of GATE voltage versus time (Figure 2). The voltage at the GATE pin rises with a slope of 0.3V/ms and the supply inrush current is set at: IINRUSH = CL • (0.3V/ms) This gate slope is designed to charge up a 1000μF ca- pacitor to 12V in 40ms, with an inrush current of 300mA. This allows the inrush current to stay under the current limit threshold (500mA) for capacitors less than 1000μF. Included in the Typical Performance Characteristics section is a graph of the Safe Operating Area for the MOSFET. It is R5 150k R6 20k ADC R1 224k C1 0.1μF R2 20k 12V 12V 4217 F01 R7 10k CT 0.1μF CL 330μF VOUT 12V 0.8A VDD UV OUT FB PG GND IMON RSET 20k RMON 20k ISET CGATE 0.1μF RGATE 1k GATE LTC4217FE OV INTVCC TIMER FLT + R3 140k R4 20k t1 t2 SLOPE = 0.3V/ms GATE OUT VDD + 6.15 VDD 4217 F02 |
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