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LTC3862HFE-1-TRPBF Datasheet(PDF) 9 Page - Linear Technology |
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LTC3862HFE-1-TRPBF Datasheet(HTML) 9 Page - Linear Technology |
9 / 40 page LTC3862-1 9 38621f PIN FUNCTIONS 3V8: Output of the Internal 3.8V LDO from INTVCC. Supply pin for the low voltage analog and digital circuits. A low ESR 1nF ceramic bypass capacitor should be connected between 3V8 and SGND, as close as possible to the IC. BLANK: Blanking Time. Floating this pin provides a nominal minimum on-time of 290ns. Connecting this pin to 3V8 provides a minimum on-time of 375ns, while connecting it to SGND provides a minimum on-time of 210ns. CLKOUT: Digital Output Used for Daisy-Chaining Multiple LTC3862-1 ICs in Multi-Phase Systems. The PHASEMODE pin voltage controls the relationship between CH1 and CH2 as well as between CH1 and CLKOUT. DMAX: Maximum Duty Cycle.This pin programs the maxi- mum duty cycle. Floating this pin provides 84% duty cycle. Connecting this pin to 3V8 provides 75% duty cycle, while connecting it to SGND provides 96% duty cycle. FB: Error Amplifier Input. The FB pin should be connected through a resistive divider network to VOUT to set the output voltage. FREQ: A resistor from FREQ to SGND sets the operating frequency. GATE1, GATE2: Gate Drive Output. The LTC3862-1 pro- vides a 10V gate drive referenced to PGND to drive a high voltage MOSFET. INTVCC: Output of the Internal 10V Low Dropout Regulator (LDO). A low ESR 4.7μF (X5R or better) ceramic bypass capacitor should be connected between INTVCC and PGND, as close as possible to the IC. ITH: Error Amplifier Output. The current comparator trip threshold increases with the ITH control voltage. The ITH pin is also used for compensating the control loop of the converter. PGND: Power Ground. Connect this pin close to the sources of the power MOSFETs. PGND should also be connected to the negative terminals of VIN and INTVCC bypass capacitors. PGND is electrically isolated from the SGND pin. The Exposed Pad of the QFN and FE packages is connected to PGND. PHASEMODE: The PHASEMODE pin voltage programs the phase relationship between CH1 and CH2 rising gate signals, as well as the phase relationship between CH1 gate signal and CLKOUT. Floating this pin or connecting it to either 3V8, or SGND changes the phase relationship between CH1, CH2 and CLKOUT. PLLFLTR: PLL Lowpass Filter Input. When synchroniz- ing to an external clock, this pin serves as the lowpass filter input for the PLL. A series resistor and capacitor connected from PLLFLTR to SGND compensate the PLL feedback loop. RUN: Run Control Input. A voltage above 1.22V on the pin turns on the IC. Forcing the pin below 1.22V causes the IC to shut down. There is a 0.5μA pull-up current for this pin. Once the RUN pin raises above 1.22V, an additional 4.5μA pull-up current is added to the pin for program- mable hysteresis. |
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