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LTC3853IUJ-PBF Datasheet(PDF) 8 Page - Linear Technology

Part # LTC3853IUJ-PBF
Description  Triple Output, Multiphase Synchronous Step-Down Controller
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC3853IUJ-PBF Datasheet(HTML) 8 Page - Linear Technology

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LTC3853
8
3853f
PIN FUNCTIONS
SENSE1+, SENSE2+, SENSE3+ (Pins 3, 5, 7): CurrentSense
Comparator Inputs. The (+) inputs to the current compara-
tors are normally connected to DCR sensing networks or
current sensing resistors. SENSE3+ common modes up
to 13.5V, allowing higher VOUT voltages on channel 3.
SENSE1, SENSE2, SENSE3(Pins 4, 6, 8):
Current
Sense Comparator Inputs. The (–) inputs to the current
comparators are connected to the outputs. SENSE3com-
mon modes up to 13.5V, allowing higher VOUT voltages
on channel 3.
VFB1, VFB2, VFB3 (Pins 9, 12, 14): Error Amplifier Feedback
Inputs. These pins receive the remotely sensed feedback
voltages for each channel from external resistive dividers
across the outputs. Connecting VFB2 to VIN through a 200k
resistor enables dual output (2 + 1) mode.
ITH1, ITH2, ITH3 (Pins 10, 13, 15): Current Control Thresh-
olds and Error Amplifier Compensation Points. Each as-
sociated channels’ current comparator tripping threshold
increases with its ITH control voltage. In dual output (2 +
1) mode, ITH1 and ITH2 need to be shorted externally.
SGND (Pin 11): Signal Ground. All small-signal compo-
nents and compensation components should connect
to this ground, which in turn connects to PGND at one
point.
PGOOD3 (Pin 16): Power Good Indicator Output for Phase
3. Open-drain logic out that is pulled to ground when any
channel output exceeds the ±7.5% regulation window, after
the internal 17μs power bad mask timer expires.
PGOOD12 (Pin 17): Power Good Indicator Output for
Phases 1 and 2. Open-drain logic out that is pulled to
ground when any channel output exceeds the ±7.5%
regulation window, after the internal 17μs power bad
mask timer expires.
INTVCC (Pin 22): Internal 5V Regulator Output. The
control circuits are powered from this voltage. Also
provides channel 3 driver power. Decouple this pin to
PGND with a minimum of 4.7μF low ESR tantalum or
ceramic capacitor.
EXTVCC(Pin23):ExternalPowerInputtoanInternalSwitch
Connected to INTVCC. This switch closes and supplies the
IC power, bypassing the internal low dropout regulator,
whenever EXTVCC is higher than 4.7V. Do not exceed 6V
on this pin and ensure VIN > VEXTVCC at all times.
VIN (Pin 24): Main Input Supply. Decouple this pin to
PGND with a capacitor (0.1μF to 1μF).
DRVCC12 (Pin 29): Driver Voltage Input for Channels 1 and
2. Do not exceed 6V on this pin. This pin must be tied to
INTVCC externally.
BG1, BG2, BG3 (Pins 30, 28, 21): Bottom Gate Driver
Outputs. These pins drive the gates of the bottom N-channel
MOSFETs between PGND and INTVCC/DRVCC12.
SW1, SW2, SW3 (Pins 31, 27, 20): Switch Node Con-
nections to Inductors. Voltage swing at these pins is from
a Schottky diode (external) voltage drop below ground
to VIN.


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