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LTC3773 Datasheet(PDF) 11 Page - Linear Technology |
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LTC3773 Datasheet(HTML) 11 Page - Linear Technology |
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11 / 32 page  LTC3773 11 3773fb PLLIN/FC (Pin 20/Pin 17): Synchronization Input to the Phase Detector and Forced Continuous Control Input. When floating, it sits around 1.6V, and the controller enters discontinuous mode operation at light load. Shorting this pin low or high for more than 20μs enables Burst Mode operation or forced continuous current mode operation, respectively. During frequency synchronization, the phase locked loop will force the controller to operate in continu- ous mode and the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal. When synchronization is not required, it is advisable to bypass the PLLIN/FC pin with a 1000pF capacitor to avoid noise coupling. CLKOUT (Pin 18 UHF Only): CLK Output. Output clock signal available to synchronize other controller ICs for additional MOSFET controller stages/phases. BG3 (Pin 21/Pin 19): Channel 3 Bottom Gate Drive. See BG1. PGND (Pin 22/Pin 39): Driver’s Power Ground. This pin connects directly to the sources of the bottom N-channel external MOSFETs and the (–) terminals of CIN.Thebackside exposed pad (QFN) must be soldered to PCB ground. VDR (Pin 23/Pin 20): Driver Supply. Provides supply to the drivers for the bottom gates. Also used for charging the bootstrap capacitors. This pin needs to be very carefully and closely decoupled to the IC’s PGND pin. If the VDR potential is lower than VCC potential by 1V, the drivers will be disabled. BG2 (Pin 24/Pin 21): Channel 2 Bottom Gate Drive. See BG1. BG1 (Pin 25/Pin 22): Channel 1 Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET between ground and VDR. SW3 (Pin 26/Pin 23): Channel 3 Switching Node. See SW1. TG3 (Pin 27/Pin 24): Channel 3 Top Gate Drive. See TG1. BOOST3 (Pin 28/Pin 25): Channel 3 Top Gate Driver Sup- ply. See BOOST1. BOOST2 (Pin 29/Pin 26): Channel 2 Top Gate Driver Sup- ply. See BOOST1. TG2 (Pin 30/Pin 27): Channel 2 Top Gate Drive. See TG1. SW2 (Pin 31/Pin 28): Channel 2 Switching Node. See SW1. SW1 (Pin 32/Pin 29): Channel 1 Switching Node. The (–) terminal of the bootstrap capacitor connects here. This pin swings from a Schottky diode (external) voltage drop below ground to VIN (where VIN is the external MOSFET supply rail). TG1 (Pin 33/Pin 30): Channel 1 Top Gate Drive. The TG1 pin drives the top N-channel MOSFET with a voltage swing equal to VDR superimposed on the switch node voltage SW. BOOST1 (Pin 34/Pin 31): Channel 1 Top Gate Driver Supply. The (+) terminal of the bootstrap capacitor connects here. This pin swings from approximately VDR up to VIN + VDR (where VIN is the external MOSFET supply rail). PGOOD (Pin 35/Pin 32): Open Drain Power Good Output. This open-drain output is pulled low during shutdown or when any of the three output voltages has been outside the PGOOD tolerance window for more than 100μs. PHASEMD (Pin 36/Pin 33): Phase Select Input. This pin controls the phase relationship between controller 1, controller 2, controller 3 and CLKOUT. When PHASEMD is floating, its value is around 1.6V, the three channels switch 120° out of phase, and CLKOUT synchronizes to the rising edge of TG1. When PHASEMD is grounded, TG1 leads CLKOUT by 60°. When PHASEMD is shorted to VCC, TG1 leads TG2, TG3, and CLKOUT by 90°, 270° and 180°, respectively. PIN FUNCTIONS (G/UHF) |
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