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54ACT16841 Datasheet(PDF) 1 Page - Texas Instruments

Part No. 54ACT16841
Description  20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

54ACT16841 Datasheet(HTML) 1 Page - Texas Instruments

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54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Members of the Texas Instruments
Widebus
™ Family
D Inputs Are TTL-Voltage Compatible
D 3-State Outputs Drive Bus Lines Directly
D Provide Extra Bus Driving/Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
D Flow-Through Architecture Optimizes
PCB Layout
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D EPIC™ (Enhanced-Performance Implanted
CMOS) 1-
µm Process
D 500-mA Typical Latch-Up Immunity at
125
°C
D Package Options Include Plastic Thin
Shrink Small-Outline (DGG) Packages,
300-mil Shrink Small-Outline (DL) Packages
Using 25-mil Center-to-Center Pin
Spacings, and 380-mil Fine-Pitch Ceramic
Flat (WD) Packages Using 25-mil
Center-to-Center Pin Spacings
description
These 20-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The ’ACT16841 can be used as two 10-bit latches
or one 20-bit latch. The 20 latches are transparent
D-type. While the latch-enable (1LE or 2LE) input
is high, the Q outputs of the corresponding 10-bit
latch follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels that
were set up at the D inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Copyright
© 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
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1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2LE
54ACT16841 . . . WD PACKAGE
74ACT16841 . . . DGG OR DL PACKAGE
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